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FEATURES Two Mask Programmable Sets of Five Reference Levels Dual 10-Bit DACs for Flicker Offset and Range Adjustment Integrated VCOM Switching Single-Supply Operation: 5.0 V Low Supply Current: 300 A Global Power Save Mode: 1 A Max Fast Settling Time for Load Change: 20 s Stable with 20 nF/100 Loads CMOS/TTL Input Levels APPLICATIONS Color TFT Cell Phones Color TFT PDAs
VL VDD VDD/2 VREF+ 10-BIT DAC A VREF-
Integrated LCD Grayscale Generator ADD8502
FUNCTIONAL BLOCK DIAGRAM
REV2 VDD VP0 VN0 R A0 V0 GND
R VN4 R
VP0 A1 V1
MUX
GENERAL DESCRIPTION
SCK
INTERFACE LOGIC
A2 DIGITAL CORE VP4 POWER SAVE LOGIC VN4 R VP4 A3
V2
The ADD8502 is an integrated, high accuracy, programmable grayscale generator. Two sets of five output reference voltages are mask programmed to 0.2% resolution. The outputs switch between the two sets of five levels. The reference levels are selected from a 512 tap resistor network using a via mask. ADD8502 includes two serially addressable, 10-bit digital-toanalog converters (DACs) and five fast, low current buffers. The dual DACs set the endpoint voltages applied to the resistor network to adjust for flicker and range. The two power save modes can reduce the total current to less than 1 A and feature fast recovery time from Shutdown/Sleep Mode. The ADD8502 accepts CMOS or TTL inputs for all controls, including the common drive circuit levels. ADD8502 operates over the industrial temperature range from -40C to +85C and is available in a space-saving 24-lead 4 mm 4 mm frame chip scale package.
DIN CS-LD
V3
PSK VN0 GS1 GS2 VDD/2 VREF+ 10-BIT DAC B VREF-
R A4 R R V4
VDD VCOM LOGIC
COM
COM_M
REV1 CM CV4
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADD8502-SPECIFICATIONS (@ V
Parameter SYSTEM ACCURACY VOUT Error Swing Error1 Mean Error2 Mean Error between Adjacent Channels3 Mean Error between V0 and V44 DAC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity5 Offset Error Gain Error OUTPUT CHARACTERISTICS Output Current Short Circuit Current Output Leakage Current in High-Z Mode Slew Rate Settling Time to 1% Slew Rate5 Settling Time to 1%5 Phase Margin VCOM SWITCHES ACTIVE IMPEDANCE COM to VDD COM to GND COM to COM_M COM to V4 MASK PROGRAMMABLE RESISTOR CHAIN Resistor Matching POWER SUPPLY Supply Voltage Supply Current Shutdown Supply Current Sleep Supply Current Shutdown Recovery Time Sleep Recovery Time LOGIC SUPPLY Logic Input Voltage Level Logic Input Current DIGITAL I/O Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Symbol
DD
= 5.0 V,
40 C TA
85 C, unless otherwise noted.)
Min Typ 3 1 3 3 3 10 0.25 0.5 0.4 0.15 Max 20 17 21 21 25 Unit mV mV mV mV mV Bits LSB LSB % of FSR % of FSR mA mA A V/s s V/s s Degrees
Conditions
(VPn - VNn) - (VPi - VNi) (VPn+ VNn)/2 - (VPi + VNi)/2)
DNL INL
IOUT ISC ILEAKAGE SR tS SR tS o Z Z Z Z
(VDD - 1 V) Short to Ground High-Z Mode RL = 100 k V0 to V4 Step Size LD =100 Series 16 nF V0 to V4 Step Size
25 60 0.01 1.25 8 0.7 8 67 25 25 25 25
1.0 12 12
See Table IV I = 20 mA
50 50 50 50
RMATCH
Any Two Segments between 512 Resistor String 4.5 190 140
1
%
VDD ISY ISY-GLB ISY-GS1-3
VDD = 5 V; No Load Full Shutdown Mode Mid 3 Buffers Shutdown Global PD to 1% V1-V3 Off to 1%
5 270 0.2 175 23 10 3.3 0.01 0.7
5.5 400 1 210 30 15 5.5 1
V A A A s s V A V V A pF
VL IVL VIH VIL IIN CIN
2.3
VL GND VIN 5.5 V
VL 1 10
0.3
NOTES 1 Swing error is a comparison of measured V OUT step versus theoretical V OUT step. Theoretical values can be found on the Mask Tap Point Option sheet. 2 Mean error is measured V OUT mean versus theoretical V OUT mean (see Figure 3). 3 Mean errors between two adjacent channels versus theoretical (see Figure 3). 4 Mean errors between V0 and V4 versus theoretical (see Figure 3). 5 Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) . Specifications subject to change without notice.
RL 100 CL 16nF VCOM
Figure 1. Slew Rate Diagram
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ADD8502
Table I. Serial Data Timing Characteristics
Parameter SCK Cycle Time SCK High Time SCK Low Time CS-LD Setup Time Data Setup Time Data Hold Time LSB SCK High to CS-LD High Minimum CS-LD High Time SCK to CS-LD Active Edge Setup Time CS-LD High to SCK Positive Edge SCK Frequency (Square Wave)
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Min Typ Max 100 45 45 20 5 5 5 10 5 10 10
Unit ns ns ns ns ns ns ns ns ns ns MHz
NOTES 1 All input signals are specified with rise/fall time -5 ns (10% to 90% of V DD) and timed from a voltage level of (VS + VIH)/2. 2 See Figure 2.
t5 t1
SCK
t9 DIN t8 CS-LD t4 C3
t6 C2
t3 X1
t2 X0
t7
t10
Figure 2. Serial Write Interface
VO VP0
SEE NOTE 2 ON SPECIFICATIONS TABLE VN0 V0 - V1 SEE NOTE 3 ON SPECIFICATIONS TABLE V1 VP1
VN1 SEE NOTE 4 ON SPECIFICATIONS TABLE VN2 V2 VP2
VN3 SEE NOTE 1 ON SPECIFICATIONS TABLE V3 VP3 VN4
V4
VP4
Figure 3. Output Wave Form Diagram
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ADD8502
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . . . . . . . . . . . . -0.3 V to +7 V VOUT to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V VCOM to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 10 sec) Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Type 24-Lead LFCSP (ACP)
1 JA
JB
2
Unit C/W
34.8
13
NOTES 1 JA is specified for worst-case conditions, i.e., JA is specified for device soldered in circuit board for surface-mount packages. 2 JB is applied for calculating the junction temperature by reference to the board temperature.
ORDERING GUIDE
Model ADD8502ACP
Temperature Range
Package Description
Package Option
-40C to +85C 24-Lead LFCSP CP-24
Available in 7" reel only.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADD8502 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADD8502
PIN CONFIGURATION
REV2 PSK GS1 GS2 VDD NC
24 23
22 21 20 19 18
VL 1 DIN 2 SCK 3 CS-LD 4 CM 5 CV4 6
7 8 9 10 11 12 PIN 1 IDENTIFIER
V0 V1 V2 V3 V4 GND
17 16 15 14 13
ADD8502
TOP VIEW
(Not to Scale)
COM_M
COM
NC
NC
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Name 1 2 3 4 5 6 7 VL DIN SCK CS-LD CM CV4 REV1 Logic Select Pin Serial Data Input Serial Clock Load Logic Control 2 for VCOM Logic Control V4 Logic Control 1 for VCOM No Connect No Connect Common Output
I/O I I I I I I I
Description Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to VDD. When CS is LOW, the input on this pin is shifted into the internal shift register on the rising edge of SCK. Accepts up to 10 MHz input. The rising edge on this clock will shift the data on DIN Pin into the internal shift registers. When CS-LD is LOW, SCK is enabled for shifting data on the DIN input into the internal shift register on the rising edge of SCK. Data is loaded MSB first. When CM is LOW, COM will output the voltage level input on COM_M. When CM is HIGH, COM levels will be determined by the input on REV1. If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is connected to COM and op amp A4 is shut down. Refer to Table II. With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level input at VDD. A LOW on REV1 will cause COM to output the voltage level input at GND. Unused Pin Unused Pin If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH, COM will output the voltage input at VDD when REV1 is HIGH and will output the voltage input at GND when REV1 is LOW. Refer to Table II. COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may be the system 3.3 V supply. Unused Pin Ground. Nominally 0 V. Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. Supply Voltage. Nominally 5 V. Unused Pin
8 9 10
NC NC COM
O
11 12 13 14 15 16 17 18 19 20
COM_M NC GND V4 V3 V2 V1 V0 VDD NC
Common System VREF No Connect Ground Output Output Output Output Output Supply No Connect
I
I O O O O O I
REV. 0
REV1
-5-
NC
ADD8502
Pin No. Mnemonic Name 21 REV2 Reference Output Select I/O Description I When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4 are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH and GS1 and GS2 are HIGH, V1-V3 are, Hi-Z state, but V0 and V4 are still connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0 and V4 switch to VN0 and VN4 when REV is LOW. When GS1 and GS2 are HIGH, the middle three output buffers are shut down and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active. When GS1 and GS2 are HIGH, the middle three output buffers are shut down and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active. When PSK is pulled LOW, the chip will be put into the full Power-Down Mode. The DACs, resistor ladder network preamps, and output buffers will all be shut down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to normal operation is within 30 s.
22
GS2
Sleep Mode Select Sleep Mode Select Global Power Shutdown
I
23
GS1 PSK
I
24
I
All digital inputs accept CMOS or TTL logic levels.
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REV. 0
Typical Performance Characteristics-ADD8502
5
VDD = 5V
250
DAC B
VDD = 5V
A
INTEGRAL NONLINEARITY - %LSB
3
DAC A
1
200
SHUTDOWN CURRENT -
384 512 640 CODE - LSB 768 896 1025
150
-1
100
-3
50
-5
0
128
256
0 40 25 TEMPERATURE - C 85
TPC 1. DAC Integral Nonlinearity
TPC 4. Shutdown Current vs. Temperature
5
190
DAC A VDD = 5V
VDD = 5V 185 A SLEEP SUPPLY CURRENT -
1024
DIFFERENTIAL NONLINEARITY - %LSB
3
180 175 170 165 160 155 40 25 TEMPERATURE - C 85
1
1
3
DAC B
5
0
128
256
384 512 640 CODE - LSB
768
896
TPC 2. DAC Differential Nonlinearity
TPC 5. Sleep Supply Current vs. Temperature
0.5 VDD = 5V 0 0.5 1.0 1.5 2.0 DAC B 2.5 DAC A
350 VDD = 5V 300 A SUPPLY CURRENT - 85 40 25 TEMPERATURE - C 250 200 150 100 50 0 40 25 TEMPERATURE - C 85
OFFSET ERROR - LSB
3.0
TPC 3. Offset Error vs. Temperature
TPC 6. Supply Current vs. Temperature
REV. 0
-7-
ADD8502
350 10.0 VDD = 5V
A
SYSTEM SUPPLY CURRENT -
SLEEP RECOVERY TIME - 2 3 4 VDD - V 5 6 7
s 9.0 8.5 8.0 7.5 7.0 40 25 TEMPERATURE - C 85
300
9.5
250
200
150
100
TPC 7. System Supply Current at Full Power
TPC 10. Sleep Recovery Time vs. Temperature
400 350
SYSTEM SUPPLY CURRENT - nA
10 VDD = 5V 8
300 250 200 150 100
0 LEAKAGE - nA 6
4
2
50 0 2.0
2
2.5
3.0
3.5
4.0
4.5 5.0 VDD - V
5.5
6.0
6.5
7.0
40
25 TEMPERATURE - C
85
TPC 8. System Supply Current at Shutdown
TPC 11. Output Leakage
28 VDD = 5V 27 s SHUTDOWN RECOVERY TIME - 26
0 VDD = 5V 0 0
VOLTAGE - 2V/DIV
25 24 23 22 21
REV2 0 0 0 V0 0
20 19 18 40 25 TEMPERATURE - C 85
0 0 0 0 0 0 0 0 0 TIME - 10 s/DIV 0 0 0 0
TPC 9. Shutdown Recovery Time vs. Temperature
TPC 12. V0 Output Swing Response to REV2
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ADD8502
25 VDD = 5V 20
300 250 200 150 100 400 350
15 RON -
10
5
50
0 40 25 TEMPERATURE - C 85
FREQUENCY
0 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 OUTPUT VOLTAGE MEAN ERROR
11 13 15
TPC 13. VCOM Switch-On-Resistance vs. Temperature
TPC 16. VOUT Swing Mean vs. Distribution
800 700 600
FREQUNECY
MEAN ERROR BETWEEN ADJACENT CHANNEL - mV
2.0
1.5 VP3-VP4 1.0
500 400 300 200 100 0 -23
0.5 VP2-VP3 0 VP1-VP2 VP0-VP1 -0.5
-18
-13
-8 -3 2 7 OUTPUT VOLTAGE - mV
12
17
22
-1.0 40 25 TEMPERATURE - C 85
TPC 14. VOUT Error Distribution
TPC 17. Mean Error between Adjacent Channel vs. Temperature
2.0
MEAN ERROR CHANNEL-TO-CHANNEL - mV
0.6 0.4 0.2 0 VN3-VN4 0.2 0.4 VN1-VN2 0.6 0.8 1.0 1.2 1.4 VN0-VN1 40 25 TEMPERATURE - C 85 VN2-VN3
1.5 1.0
SWING ERROR - mV
V0
0.5 0 -0.5 -1.0 -1.5 -2.0
V1 V2 V3
V4 -2.5 40 25 TEMPERATURE - C 85
TPC 15. Swing Error vs. Temperature
TPC 18. Mean Error between Adjacent Channel vs. Temperature
REV. 0
-9-
ADD8502
2.0 1.5 VP0-VP4 9 RISING EDGE 8
TIME - s
10 VDD = 5V
MEAN ERROR V0-V4 - mV
1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 40 25 TEMPERATURE - C 85 4 40 VN0-VN4 5
7
6 FALLING EDGE
45 TEMPERATURE - C
125
TPC 19. Mean Error between V0 and V4 vs. Temperature
TPC 22. Settling Time at VOUT vs. Temperature
0 VL = 2.5V 0
5
SOURCE 4 SINK 3
0
VOLTAGE - 500mV/DIV
0 VTH HIGH 0 VTH LOW 0 0
OUTPUT VOLTAGE - V
2
1
0 0 0 0 0 0 0 0 0 TIME - 500mV/DIV 0 0 0 0
0 0 20 40 60 OUTPUT CURRENT - mA 80
TPC 20. REV1 Hysteresis
TPC 23. Output Current Source and Sink
1.40 VDD = 5V 1.35 1.30 SLEW RATE - V/ s SLEW RATE FALLING 1.25 1.20 SLEW RATE RISING 1.15 1.10 1.05 1.00 40 25 TEMPERATURE - C 85
TPC 21. Slew Rate vs. Temperature
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ADD8502
OPERATION Transfer Function
The transfer function for the ADD8502 is given in the following equations: 1. Digital-to-analog transfer function for DAC A. An output can be derived from Equation 1 as:
VOUTA = 4.941 V VOUTB = 0.244 V VTX = 4.831 V Equations 1-3 will provide a theoretical calculation of the outputs. The actual will vary with load, process, and architecture. See Specifications table.
SERIAL INTERFACE
D V VOUTA = DD 1 + A 2 1024
(1)
2. Digital-to-analog transfer function for DAC B. An output can be derived from Equation 2 as:
D V VOUTB = B DD 1024 2
(2)
The ADD8502 has a 3-wire serial interface (CS-LD, SCK, and DIN). The writing sequence begins by bringing the CS-LD line LOW. Data on the DIN line is clocked into the 16-bit shift register on the rising edge of SCK. The serial clock frequency can be as high as 10 MHz. When the last data bit is clocked in, CS-LD line needs to be brought HIGH to load the DAC registers and the operation mode is dependent upon the control bits.
Input Shift Register
Where DA and DB are decimal equivalents of the binary codes that are loaded to the DAC Register from 0 to 1023. 3. Using any programmed tap point from the 512 resistor string, the system output can be derived from Equation 3: VTX = (VOUTA - VOUTB ) TX + VOUTB 512 (3)
The input shift register is 16 bits wide (see Figure 4). The first four control bits (C3, C2, C1, and C0) are used to set the different operating modes of the device. The next 10 bits are the data bits and the last two bits are "Don't Cares." This composes a full word that is transferred to the DAC register on the rising edge of CS-LD. In a normal write sequence, the CS-LD line is kept LOW for at least 16 rising edges of SCK and then it is brought HIGH to update the DACs. However, if CS-LD is brought HIGH before the 16th rising edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operation mode occurs.
Where TX is any tap point of the 512 resistor string. It is mask programmable. VTX is the voltage output at any output (VO, ... V4) and will switch between two voltages depending on the mask programmed tap points. Example: VDD = 5 V, DA = 1,000, DB = 100, and TX = 500.
DB15 (MSB) C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1
DB0 (LSB) X0
CONTROL BITS
DATA BITS
DON'T CARE
Figure 4. Input Register Contents
REV. 0
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ADD8502
Table II. DAC Control Function
Control Code C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
Status No Change Load DAC A Load DAC B
Input Register Status No Update No Update No Update Not Used Not Used Not Used Not Used Not Used
DAC Register (Sleep/Wake) No Change No Change No Change
Power-Down Status Comments No operation; power-down status unchanged (part stays in Wake or Sleep Mode). Load input Register A with data. DAC outputs unchanged. Power-down status unchanged. Load input Register B with data. DAC outputs unchanged. Power-down status unchanged.
No Change
Update Outputs
Wake
Load both DAC registers with existing contents of input registers. Update DAC outputs. Part wakes up. Load input Register A. Load DAC registers with new contents of input register A and existing contents of Register B. Update DAC outputs. Part wakes up. Load input Register B. Load DAC registers with new contents of input Register B and existing contents of Register A. Update DAC outputs. Part wakes up.
1
0
0
1
Load DAC A
Update Outputs
Wake
1
0
1
0
Load DAC B
Update Outputs
Wake
1 1 1
0 1 1
1 0 0
1 0 1 No Change
Not Used Not Used No Update Wake Part wakes up. Input and DAC registers unchanged. DAC outputs reflect existing contents of DAC registers. Power down the IC, put in into Sleep Mode. Load both input registers. Load both DAC registers with new contents of input registers. Update DAC outputs. Part wakes up. Access to the DAC register is controlled by the control codes, C0 to C3. The user can update both DACs simultaneously as well as individually. It depends on the selected control codes to update individual output or both outputs simultaneously.
Initial Power-Up Condition
1 1
1 1
1 1
0 1
No Change Load DACs A, B with Same 10-Bit Code
No Update Update Outputs
Sleep Wake
Modes of Operation
The ADD8502 has various modes of operation, such as updating both DACs simultaneously or changing the power-down status (Sleep/Wake). These are selected by writing the appropriate 4-bit control code (C0-C3). The details for each mode are summarized in Table II.
Low Power Serial Interface
To reduce the power consumption of the device ever further, the interface only powers up fully when the device is being written to. As soon as the 16-bit control word has been written to the part, the SCK and DIN input buffers are powered down. They only power up again following a falling edge of CS-LD.
Double-Buffered Interface
The ADD8502 has preset DAC conditions when its initially powered on. The DACs are loaded with 1110 1011 11 for the upper DAC and 0000 1010 00 for the lower DAC. The part is powered up in a normal operation mode (Wake Status).
Power-Down Modes
The ADD8502 has double-buffered interfaces consisting of two banks of registers: input and DAC. The input register is connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string.
The ADD8502 has two shutdown modes. One mode is to fully shut down the device using PSK or the digital serial control code, and the other mode is to shut down V1 to V3 buffers using GS1 and GS2. See Table III for the priority of the shutdown control functions.
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ADD8502
The ADD8502 will have a quiescent current less than 1 A when it is fully shut down and all output buffers are switched to a high impedance state. The only active circuitries are the digital logics and the latches for the serial control. When the device is brought back from Sleep Mode to normal operation, it will use the last serial word to update the DACs or a new control code or data if any was loaded when the part was in Sleep Mode; i.e., the contents of the input register, DAC register, and power-down status shown in Table II is retained as long as VDD and VL are on. The second power save mode (mid 3 buffers are shut down) is using GS1 and GS2. In a condition where both GS1 and GS2 logics are HIGH, the output buffers (V1, V2, and V3) are shut down and switched into a high impedance state.
Table III. Shutdown Control Function VCOM Logic
VCOM operation is described in Table IV. The VCOM logic is always active and its logic inputs are CM, REV1, and CV4. When CM is LOW, COM is connected to COM_M. When CM is HIGH, COM is determined by the logic input of REV1. If REV1 is HIGH, COM is connected to VDD. When REV1 is LOW, COM is connected to GND. CV4 controls the V4 output. If CV4 goes LOW, V4 is connected to COM and A4 is shut down with its output in a Hi-Z state. When CV4 is HIGH, the switch connecting V4 to COM is open and A4 is in normal operation mode.
Table IV. VCOM Logic Control
Inputs CM L L H H H H
X = Don't Care
Outputs REV1 X X L H L H CV4 L H L L H H VCOM COM_M COM_M GND VDD GND VDD V4 COM A4 COM COM A4 A4
PSK H H H H H L
Serial Control Wake Wake Wake Wake Sleep X
GS1 L L H H X X
GS2 L H L H X X
Operation Mode Normal Operation Normal Operation Normal Operation Mid 3 Buffers are Shutdown Full Shutdown Full Shutdown
X = Don't Care
REV. 0
-13-
ADD8502
VL VDD
SCK
LOGIC LEVEL TRANSLATOR
DIN
LOGIC LEVEL TRANSLATOR
V0
CS-LD
LOGIC LEVEL TRANSLATOR
V1
V2 PSK LOGIC LEVEL TRANSLATOR
V3 GS1 LOGIC LEVEL TRANSLATOR ADD8502 CORE V4
GS2
LOGIC LEVEL TRANSLATOR COM
REV1
LOGIC LEVEL TRANSLATOR
REV2
LOGIC LEVEL TRANSLATOR
COM_M
CM
LOGIC LEVEL TRANSLATOR
CV4
LOGIC LEVEL TRANSLATOR
VL
VDD
GND
Figure 5. CST ESD and Logic Level Translation Scheme
ADD8502 Description
*
* *
The ADD8502 uses logic level translators to convert external logic levels to levels suitable for use in the ADD8502 core. The logic level translators are intended to be powered from the same supply voltage as is used to power the external logic driving the ADD8502. VDD may be powered down while normal voltages are present on the VL and logic input pins. VDD and VL are independent and can be in the range 0 V to 5.5 V. * * * *
No damage to the digital inputs will occur with applied voltages up to 7 V (see Absolute Maximum Ratings section of data sheet). No current will flow between VDD and VL under normal operating conditions. Logic voltages can be present on the logic input pins even if VL is powered down. Inputs are limited by max supply rating of 7 V. Digital input pins have ESD protection connected to GND. All other input and output pins have ESD protection connected to GND and VDD.
* *
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ADD8502
ADD8502-000 MASK OPTION
DAC A VOUTA
Table V. Default Power-Up Conditions
VP0 VP1
VN4 VN3 VN2 VN1 VN0
DAC Setpoints (0 D 1023) Decimal Code Upper DAC Lower DAC 943 40 Voltage 4.8022 0.0977 Unit V V
VP2 VP3 VP4
Resistor Tap Points (0 X 512) Tap Point VP0 VP1 VP2 VP3 VP4 VN0 VN1 VN2 VN3 VN4
Supply voltage = 5 V
Voltage 4.2325 2.5878 1.9630 1.3565 0.1252 0.3825 2.0732 2.7624 3.4699 4.7747
Unit
DAC B
450 271 203 137 3 31 215 290 367 509
V V V V V V V V V V
VOUTB
Figrue 6. Tap Point References
Tap point voltages can be derived from the following equation: X [VOUTA - VOUTB ] 512 Where VOUTA and VOUTB can be derived from the transfer functions under the Operation Section of the datasheet. Vx = VOUTB + The ADD8502 uses a single resistor string consisting of 512 individual elements. Both sets of reference voltages (VP0-VP4, VN0-VN4) are generated from this single string. Two separate resistor networks are shown to demonstrate the tap points, which are changeable by mask option and completely independent of each other.
REV. 0
-15-
ADD8502
OUTLINE DIMENSIONS 24-Lead Frame Chip Scale Package [LFCSP] 4x4 mm Body (CP-24)
4.0 BSC SQ 0.60 MAX 0.60 MAX
19 18 24 1
0.25 MIN
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
BOTTOM VIEW
13 12 7 6
2.25 1.70 0.75
1.00 0.90 0.85 0.25 REF
12 MAX
0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 COPLANARITY 0.08
2.50 REF
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
-16-
REV. 0
PRINTED IN U.S.A.
C02944-0-8/02(0)

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